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s6b 071 9 160 seg / 1 05 com seg driver & controller for stn lcd j an . 2000 . ver. 0. 4 prepared by: koo-hyung, jung chunggh@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 2 S6B0719 specification revision history version content date 0.0 - original feb. 1999 0.1 - append pad center coordinate (refer to t able 2) - append display data ram map (refer to f igure 8) mar. 1999 0.2 - modify display data ram map (refer to f igure 8) - append reference circuit examples (refer to p age 22) may. 1999 0.3 - change the low power consumption v0 = 13v -> 15v (refer to page 1) - modify page address circuit description ; db3, db2 and db1 are ? h ? , but db1 is ? l ? -> db3, db2 and db0 are ? h ? , but db1 is ? l ? (refer to page 20) - modify set partial display duty ratio (refer to page 27) - add partial duty changing ? waiting for discharging the lcd power levels (refer to figure 34) jun. 1999 0.4 - change the condition of power consumption : (vdd = 3v, x6 boosting, v0 = 15v) ? (vdd = 3v, x5 boosting, v0 = 13v) (refer to page 1) - change the absolute maximum ratings of v0 and vout : 20v ? 17v (refer to page 50) - change the operating voltage of v0 and vout : 17v ? 15v (refer to page 1 and 51) - change the operating voltage of vdd : (2.4 to 5.5v) ? (2.4 to 3.6v) (refer to page 1 and 51) - modify figure20 (refer to page 24) jan.2000
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 block diagram ................................ ................................ ................................ ................................ ............... 2 pad configuration ................................ ................................ ................................ ................................ ....... 3 pad center coordinates ................................ ................................ ................................ ............................ 4 pin description ................................ ................................ ................................ ................................ .............. 6 functional description ................................ ................................ ................................ ............................ 11 microprocessor interface ................................ ................................ ................................ ............. 11 display data ram (ddram) ................................ ................................ ................................ .................. 14 lcd display circuits ................................ ................................ ................................ ............................ 17 lcd driver circuit ................................ ................................ ................................ ............................... 19 power supply circuits ................................ ................................ ................................ ...................... 21 reference circuit examples ................................ ................................ ................................ ........... 26 reset circuit ................................ ................................ ................................ ................................ ......... 28 instruction description ................................ ................................ ................................ ........................... 29 specifications ................................ ................................ ................................ ................................ .............. 50 absolute maximum ratings ................................ ................................ ................................ ............... 50 dc characteristics ................................ ................................ ................................ ............................. 51 ac characteristics ................................ ................................ ................................ ............................. 55 reference applications ................................ ................................ ................................ ........................... 59 microprocessor interface ................................ ................................ ................................ ............. 59 connections between S6B0719 and lcd panel ................................ ................................ ............ 60
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 1 introduction the S6B0719 is a driver & controller lsi for graphic dot-matrix liquid crystal display systems. it contains 105 common and 160 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8- bit parallel display data and stores in an on-chip display data ram of 105 x 160 bits. it provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external-operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 105 common o utputs / 160 segment outputs applicable duty-ratios programmable duty ratio applicable lcd bias maximum display area 1/9 to 1/105 1/4 to 1/11 105 160 - various partial display - partial window moving & data scrolling on-chip display data ram - capaci ty: 105 x 160 = 16,800 bits - bit data "1": a dot of display is illuminated - bit data "0": a dot of display is not illuminated microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series - serial interface (only writ e operation) available on-chip low power analog circuit - on-chip oscillator circuit - voltage converter (x3, x4, x5 or x6) - voltage regulator (temperature coefficient: -0.05%/ c or external input) - on-chip electronic contrast control function (64 steps) - voltage follower (lcd bias: 1/4 to 1/11) operating voltage range - supply voltage (v dd ): 2.4 to 3.6 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 15 .0 v low power consumption - tbd m a typ. (v dd = 3v, x6 boosting, v0 = 13 v, internal power supply on and display off) - tbd m a max. (during power save [standby] mode ) package type - gold bumped chip or tcp
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 2 block diagram ms cl sync m frs fr vdd v0 v1 v2 v3 v4 vss hpmb v0 vr intrs vext ref vout c1- c1+ c2- c2+ c3+ c4+ c5+ vci v/c circuit v / r rcircuit v/ f circuit 10 6 common driver circuits mpu interface (parallel & serial) instruction decoder & register status register bus holder column address circuit line address circuit page address circuit display data ram 105 x 1 6 0 = 16,8 00 bits segment controller static driver display timing generator circuit common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) rw_wr e_rd rs cs2 cs1b ps c68 resetb coms com 10 3 : : : com0 coms seg 15 9 seg 15 8 seg 15 7 : : seg2 seg1 seg0 oscillator 1 6 0 segment driver circuits figure 1 . block diagram
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 3 pad configuration ee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee ee y 167 330 166 331 137 360 136 1 s6b 071 9 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee *2 *1 *3 figure 2 . S6B0719 chip configuration table 1 . S6B0719 pad dimensions size item pad no. x y unit chip size - 9370 2220 29 to 108 70 (m in. ) pad pitch 1 to 28, 109 to 136, 137 to 360 54 (m in. ) 30 to 107 60 78 138 to 165, 332 to 359 78 44 3 to 27, 110 to 134 169 to 328 44 78 1, 2, 28, 29, 108, 109, 135, 136, 167, 168, 329 and 330 70 78 bumped ` pad size 137, 166, 331 and 360 78 70 bumped pad height 1 to 360 14 (typ.) m m 42 um 108 um 42 um 108 um (-3131.6,622.75) *2 : ilb align key 1 30 um 30 um 30 um 30 um 30 um 30 um (-4033.05,-374.4) *1 : cog align key *3 : ilb align key 2 (4135.6,-633.0) 42 um 108 um 42 um 108 um
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 4 pad center coordinates table 2 . pad center coordinates [unit: m m] no name x y no name x y no name x y no name x y 1 dummy -4453 -985 51 rw_wr -1225 -985 101 vr 2275 -985 151 com13 4560 -27 2 dummy -4373 -985 52 e_rd -1155 -985 102 vss 2345 -985 152 com12 4560 27 3 com80 -4293 -985 53 vdd -1085 -985 103 ref 2415 -985 153 com11 4560 81 4 com81 -4239 -985 54 db0 -1015 -985 104 vext 2485 -985 154 com10 4560 135 5 com82 -4185 -985 55 db1 -945 -985 105 vdd 2555 -985 155 com9 4560 189 6 com83 -4131 -985 56 db2 -875 -985 106 intrs 2625 -985 156 com8 4560 243 7 com84 -4077 -985 57 db3 -805 -985 107 vss 2695 -985 157 com7 4560 297 8 com85 -4023 -985 58 db4 -735 -985 108 dummy 2775 -985 158 com6 4560 351 9 com86 -3969 -985 59 db5 -665 -985 109 dummy 2917 -985 159 com5 4560 405 10 com87 -3915 -985 60 db6 -595 -985 110 com51 2997 -985 160 com4 4560 459 11 com88 -3861 -985 61 db7 -525 -985 111 com50 3051 -985 161 com3 4560 513 12 com89 -3807 -985 62 vdd -455 -985 112 com49 3105 -985 162 com2 4560 567 13 com90 -3753 -985 63 vdd -385 -985 113 com48 3159 -985 163 com1 4560 621 14 com91 -3699 -985 64 vdd -315 -985 114 com47 3213 -985 164 com0 4560 675 15 com92 -3645 -985 65 vdd -245 -985 115 com46 3267 -985 165 coms 4560 729 16 com93 -3591 -985 66 vci -175 -985 116 com45 3321 -985 166 dummy 4560 809 17 com94 -3537 -985 67 vci -105 -985 117 com44 3375 -985 167 dummy 4453 985 18 com95 -3483 -985 68 vss -35 -985 118 com43 3429 -985 168 dummy 4373 985 19 com96 -3429 -985 69 vss 35 -985 119 com42 3483 -985 169 seg0 4293 985 20 com97 -3375 -985 70 vss 105 -985 120 com41 3537 -985 170 seg1 4239 985 21 com98 -3321 -985 71 vss 175 -985 121 com40 3591 -985 171 seg2 4185 985 22 com99 -3267 -985 72 vout 245 -985 122 com39 3645 -985 172 seg3 4131 985 23 com100 -3213 -985 73 vout 315 -985 123 com38 3699 -985 173 seg4 4077 985 24 com101 -3159 -985 74 c5+ 385 -985 124 com37 3753 -985 174 seg5 4023 985 25 com102 -3105 -985 75 c5+ 455 -985 125 com36 3807 -985 175 seg6 3969 985 26 com103 -3051 -985 76 c3+ 525 -985 126 com35 3861 -985 176 seg7 3915 985 27 coms -2997 -985 77 c3+ 595 -985 127 com34 3915 -985 177 seg8 3861 985 28 dummy -2917 -985 78 c1- 665 -985 128 com33 3969 -985 178 seg9 3807 985 29 dummy -2775 -985 79 c1- 735 -985 129 com32 4023 -985 179 seg10 3753 985 30 frs -2695 -985 80 c1+ 805 -985 130 com31 4077 -985 180 seg11 3699 985 31 fr -2625 -985 81 c1+ 875 -985 131 com30 4131 -985 181 seg12 3645 985 32 test1 -2555 -985 82 c2+ 945 -985 132 com29 4185 -985 182 seg13 3591 985 33 test2 -2485 -985 83 c2+ 1015 -985 133 com28 4239 -985 183 seg14 3537 985 34 test3 -2415 -985 84 c2- 1085 -985 134 com27 4293 -985 184 seg15 3483 985 35 cl -2345 -985 85 c2- 1155 -985 135 dummy 4373 -985 185 seg16 3429 985 36 m -2275 -985 86 c4+ 1225 -985 136 dummy 4453 -985 186 seg17 3375 985 37 sync -2205 -985 87 c4+ 1295 -985 137 dummy 4560 -809 187 seg18 3321 985 38 vss -2135 -985 88 vss 1365 -985 138 com26 4560 -729 188 seg19 3267 985 39 hpmb -2065 -985 89 vss 1435 -985 139 com25 4560 -675 189 seg20 3213 985 40 ms -1995 -985 90 v4 1505 -985 140 com24 4560 -621 190 seg21 3159 985 41 vdd -1925 -985 91 v4 1575 -985 141 com23 4560 -567 191 seg22 3105 985 42 ps -1855 -985 92 v3 1645 -985 142 com22 4560 -513 192 seg23 3051 985 43 c68 -1785 -985 93 v3 1715 -985 143 com21 4560 -459 193 seg24 2997 985 44 vss -1715 -985 94 v2 1785 -985 144 com20 4560 -405 194 seg25 2943 985 45 cs1b -1645 -985 95 v2 1855 -985 145 com19 4560 -351 195 seg26 2889 985 46 cs2 -1575 -985 96 v1 1925 -985 146 com18 4560 -297 196 seg27 2835 985 47 vdd -1505 -985 97 v1 1995 -985 147 com17 4560 -243 197 seg28 2781 985 48 resetb -1435 -985 98 v0 2065 -985 148 com16 4560 -189 198 seg29 2727 985 49 rs -1365 -985 99 v0 2135 -985 149 com15 4560 -135 199 seg30 2673 985 50 vss -1295 -985 100 vr 2205 -985 150 com14 4560 -81 200 seg31 2619 985
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 5 table 2 (continued) [unit: m m] no name x y no name x y no name x y no name x y 201 seg32 2565 985 251 seg82 -135 985 301 seg132 -2835 985 351 com71 -4560 -297 202 seg33 2511 985 252 seg83 -189 985 302 seg133 -2889 985 352 com72 -4560 -351 203 seg34 2457 985 253 seg84 -243 985 303 seg134 -2943 985 353 com73 -4560 -405 204 seg35 2403 985 254 seg85 -297 985 304 seg135 -2997 985 354 com74 -4560 -459 205 seg36 2349 985 255 seg86 -351 985 305 seg136 -3051 985 355 com75 -4560 -513 206 seg37 2295 985 256 seg87 -405 985 306 seg137 -3105 985 356 com76 -4560 -567 207 seg38 2241 985 257 seg88 -459 985 307 seg138 -3159 985 357 com77 -4560 -621 208 seg39 2187 985 258 seg89 -513 985 308 seg139 -3213 985 358 com78 -4560 -675 209 seg40 2133 985 259 seg90 -567 985 309 seg140 -3267 985 359 com79 -4560 -729 210 seg41 2079 985 260 seg91 -621 985 310 seg141 -3321 985 360 dummy -4560 -809 211 seg42 2025 985 261 seg92 -675 985 311 seg142 -3375 985 212 seg43 1971 985 262 seg93 -729 985 312 seg143 -3429 985 213 seg44 1917 985 263 seg94 -783 985 313 seg144 -3483 985 214 seg45 1863 985 264 seg95 -837 985 314 seg145 -3537 985 215 seg46 1809 985 265 seg96 -891 985 315 seg146 -3591 985 216 seg47 1755 985 266 seg97 -945 985 316 seg147 -3645 985 217 seg48 1701 985 267 seg98 -999 985 317 seg148 -3699 985 218 seg49 1647 985 268 seg99 -1053 985 318 seg149 -3753 985 219 seg50 1593 985 269 seg100 -1107 985 319 seg150 -3807 985 220 seg51 1539 985 270 seg101 -1161 985 320 seg151 -3861 985 221 seg52 1485 985 271 seg102 -1215 985 321 seg152 -3915 985 222 seg53 1431 985 272 seg103 -1269 985 322 seg153 -3969 985 223 seg54 1377 985 273 seg104 -1323 985 323 seg154 -4023 985 224 seg55 1323 985 274 seg105 -1377 985 324 seg155 -4077 985 225 seg56 1269 985 275 seg106 -1431 985 325 seg156 -4131 985 226 seg57 1215 985 276 seg107 -1485 985 326 seg157 -4185 985 227 seg58 1161 985 277 seg108 -1539 985 327 seg158 -4239 985 228 seg59 1107 985 278 seg109 -1593 985 328 seg159 -4293 985 229 seg60 1053 985 279 seg110 -1647 985 329 dummy -4373 985 230 seg61 999 985 280 seg111 -1701 985 330 dummy -4453 985 231 seg62 945 985 281 seg112 -1755 985 331 dummy -4560 809 232 seg63 891 985 282 seg113 -1809 985 332 com52 -4560 729 233 seg64 837 985 283 seg114 -1863 985 333 com53 -4560 675 234 seg65 783 985 284 seg115 -1917 985 334 com54 -4560 621 235 seg66 729 985 285 seg116 -1971 985 335 com55 -4560 567 236 seg67 675 985 286 seg117 -2025 985 336 com56 -4560 513 237 seg68 621 985 287 seg118 -2079 985 337 com57 -4560 459 238 seg69 567 985 288 seg119 -2133 985 338 com58 -4560 405 239 seg70 513 985 289 seg120 -2187 985 339 com59 -4560 351 240 seg71 459 985 290 seg121 -2241 985 340 com60 -4560 297 241 seg72 405 985 291 seg122 -2295 985 341 com61 -4560 243 242 seg73 351 985 292 seg123 -2349 985 342 com62 -4560 189 243 seg74 297 985 293 seg124 -2403 985 343 com63 -4560 135 244 seg75 243 985 294 seg125 -2457 985 344 com64 -4560 81 245 seg76 189 985 295 seg126 -2511 985 345 com65 -4560 27 246 seg77 135 985 296 seg127 -2565 985 346 com66 -4560 -27 247 seg78 81 985 297 seg128 -2619 985 347 com67 -4560 -81 248 seg79 27 985 298 seg129 -2673 985 348 com68 -4560 -135 249 seg80 -27 985 299 seg130 -2727 985 349 com69 -4560 -189 250 seg81 -81 985 300 seg131 -2781 985 350 com70 -4560 -243
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 6 pin description table 3 . power s upply p ins name i/o description v dd supply power supply vss supply ground lcd drivers supply voltages the voltage determined by lcd pixel is impedance-converted by an operational amplifier for application. voltages should have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 vss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/n bias (n-1)/n x v0 (n-2)/n x v0 2/n x v0 1/n x v0 v0 v1 v2 v3 v4 i/o note : *n = 4 to 11 table 4 . lcd driver supply p ins name i/o description c1- , c2- i/ o capacitor negative connection pin s for voltage converter c1+ , c2+ c3+, c4+ c5+ i/ o capacitor positive connection pin s for voltage converter vout i/o voltage converter input/output pin vci i voltage converter input voltage pin voltages should have the following relationship: vdd vci v0 vr i v0 voltage adjustment pin it is valid only when on-chip resistors are not used. (intrs = ? l ? ) ref i selects the external v ref voltage via vext pin - ref = "l": using the external v ref - ref = "h": using the internal v ref vext i externally input reference voltage (vref) for the internal voltage regulator. it is valid only when ref is ? l ? .
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 7 table 5 . system control p ins name i/o description master / slave operations select pin - ms = "h": master operation - ms = "l": slave operation the following table depends on the ms status. internal analog circuits display timing signals ms oscillator power supply cl sync m h enabled enabled output output output l disabled disabled input input input ms i cl i/o display clock input / output pin when the S6B0719 is used in master / slave mode (multi-chip), the cl pins must be connected each other. sync i/o display sync input / output pin when the S6B0719 is used in master/slave mode (multi-chip), the sync pins must be connected each other. m i/o lcd ac input / output pin when the S6B0719 is used in master/slave mode (multi-chip), the m pins must be connected each other. fr o static driver common output pin this pin is used together with the frs pin. frs o static driver segment output pin this pin is used together with the fr pin. intrs i internal resistors select pin this pin selects the resistors for adjusting v0 voltage level. - intrs = "h ? : use the internal resistors. - intrs = "l ? : use the external resistors. vr pin and external resistive divider control v0 voltage . hpmb i power control pin of the power supplies circuit for lcd driver - hpmb = "l": high power mode - hpmb = "h": normal mode this pin is valid in master operation. test1 to test 3 i test pins don ? t use these pins. note: dummy ? these pins should be opened (floated).
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 8 table 6 . microprocessor interface p ins name i/o description resetb i reset input pin when resetb is ? l ? , initialization is executed. parallel / serial data input select input ps interface mode data / instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs sid (db7) write only sclk (db6) ps i *note: when ps is ? l ? , db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either ? h ? or ? l ? . c68 i microprocessor interface select input pin - c68 = "h": 6800-series mpu interface - c68 = "l": 8080-series mpu interface cs1b cs2 i chip select input pins data / instruction i/o is enabled only when cs1b is ? l ? and cs2 is ? h ? . when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wr description h 6800-series rw read/write control input pin - rw = ? h ? : read - rw = ? l ? : write l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 9 table 6. (continued) name i/o description read / write execution control pin c68 mpu type e_rd description h 6800-series e read / write control input pin - rw = ? h ? : when e is ? h ? , db0 to db7 are in an output status. - rw = ? l ? : the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is ? l ? , db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid). when chip select is not active, db0 to db7 may be high impedance.
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 10 table 7 . lcd driver output pins name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m normal display reverse display h h v0 v2 h l vss v3 l h v2 v0 l l v3 vss power save mode vss vss seg0 to seg 15 9 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m common driver output voltage h h vss h l v0 l h v1 l l v4 power save mode vss com0 to com 10 3 o coms o common output for the icons the output signals of two pins are same. when not used, these pins should be left open.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 11 functional description microprocessor interface chip select input there are cs1b and cs2 pins for c hip s election. the S6B0719 can interface with an mpu only when cs1b is ? l ? and cs2 is ? h ? . when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface the S6B0719 has three types of interface with an mpu, which are one serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table 8. table 8 . parallel / serial interface mode. ps type cs1b cs2 c68 interface mode h 6800-series mpu mode h parallel cs1b cs2 l 8080-series mpu mode l serial cs1b cs2 * serial-mode * : don't care parallel interface (ps = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 10. table 9 . microprocessor selection for parallel interface c68 cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800-series l cs1b cs2 rs /rd /wr db0 to db7 8080-series table 10 . parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 12 serial interface (ps = "l") when the S6B0719 is active, serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . serial interface timing busy flag the b usy f lag indicates whether the S6B0719 is operating or not. when db7 is ? h ? in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 13 data transfer the S6B0719 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 4. and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 5. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 4 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 figure 5 . read timing
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 14 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 105 -row by 160-column addressable array. each pixel can be selected when the page and column addresses are specified. the 105 rows are divided into 1 3 pages of 8 lines and the 13th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com0 - - com1 - - com2 - - com3 - - com4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay d ata ram lcd display figure 6 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in f igure 8 . it incorporates 4-bit p age a ddress register changed by only the ? set page ? instruction. page address 1 3 (db3 , db2 and db0 are ? h ? , but db1 is ? l ? ) is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a line address corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 7. it incorporates 7-bit line address register changed by only the i nitial d isplay l ine instruction and 7-bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine a ddress for transferring the 160-bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 15 column address circuit column a ddress circuit has an 8 -bit preset counter that provides c olumn a ddress to the display data ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 8 -bit [y 7 :y0] is updated. and, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. however, the counter is not incremented and locked if a non-existing address above 9f h. it is unlocked if a column address is set again by s et column address msb / lsb instruction. and t he c olumn a ddress counter is independent of page address register. adc s elect instruction makes it possible to invert the relationship between the c olumn a ddress and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc s elect instruction. r efer to the following figure 7 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 15 6 seg 15 7 seg 15 8 seg 15 9 column a ddress [y 7 :y0] 00h 01h 02h 03h ... ... 9c h 9d h 9e h 9f h display data 1 0 1 0 1 1 0 0 lcd panel d isplay ( adc = 0 ) ... ... lcd p anel d isplay ( adc = 1 ) ... ... figure 7 . the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse d isplay o n / o ff and e ntire d isplay on / off instructions without changing the data in the display data ram.
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 16 line address com output page address db3 db0 db1 db2 data initial start line address = 08h 02 page 0 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 00h 01h 02h 03h 04h 05h 06h 07h page 1 0 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh page 2 0 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 3 0 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 9 1 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page 10 1 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 11 1 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 12 1 0 0 1 db0 db1 db2 db3 db4 db5 db6 db7 03 01 04 05 page 13 1 1 0 1 db0 - - - - - - - - - 9c 9d 9a 9b 9e 9f 02 03 00 01 04 05 - - - - - - - - 9c 9d 9a 9b 9e 9f adc=0 adc=1 column address 00 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com72 com73 com74 com75 com76 com77 com78 com79 com80 com81 com82 com83 com84 com85 com86 com87 com88 com89 com90 com91 com92 com93 com94 com95 com96 com97 com98 com99 com100 com101 com102 com103 coms lcd segment output - - - - - - - - seg0 seg1 seg2 seg3 seg4 seg5 seg154 seg155 seg156 seg157 seg158 seg159 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh 60h 61h 62h 63h 64h 65h 66h 67h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh 1/105 duty 1/97 duty start = 08h end = 07h figure 8 . display data ram map
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 17 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock (cl) and the display data latch circuit in synchronization latches the 160-bit display data with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame or the line changes the phase of m by setting internal instruction. driving waveform and internal timing signal are shown in figure 10. in a multi ple -chip configuration , the slave chip requires the cl, m and sync signals from the master. table 11 shows the cl, sync, and m status. table 11 . master and slave timing signal status operation mode oscillator cl sync m master on (internal clock used) output output output slave off (external clock used) input input input
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 18 fr m 84 85 1 2 3 4 5 6 7 8 9 10 11 12 78 79 80 81 82 83 84 85 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 9 . 2-frame ac driving waveform (duty ratio = 1/ 8 5) fr m 84 85 1 2 3 4 5 6 7 8 9 10 11 12 78 79 80 81 82 83 84 85 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 10 . n-line inversion driving waveform (n = 5, duty ratio = 1/ 8 5)
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 19 lcd driver circuit 106-channel common driver and 160-channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m signal. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg2 seg1 seg0 com2 com0 com1 m v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss figure 11 . segment and common timing
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 20 partial display on lcd the S6B0719 realizes the partial display function on lcd with low-duty driving for saving power consumption and showing the various display duties. to show the various display duties on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjusting the lcd driving voltages -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 12 . reference example for partial display (display duty = 25) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 13 . partial display (partial display duty = 9, initial com0 = 0) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 14 . moving display (partial display duty = 9, initial com0 = 8)
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 21 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low- power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 12 shows the referenced combinations in using p ower s upply circuits. table 12 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on external input open open only the external power supply circuits are used 0 0 0 off off off open external input external input
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 22 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ? set dc-dc step-up ? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + vout = 3 vci c1 - + c1 - + vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + c1 - + vout = 4 vci figure 15 . three times boosting circuit figure 16 . four times boosting circuit vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + c1 - + c1 - + c1 - + c1 - + vout = 5 vci vout = 6 vci c1 - + figure 17 . five times boosting circuit figure 18 . six times boosting circuit
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 23 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure 19 , it is necessary to be applied internally or externally. for the eq. 6-1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 6-2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 13 . v0 = { 1 + ( rb / ra) } x v ev [v] ------ (eq. 6-1) v ev = { 1 - (63 - a ) / 200 } x 2.0 = 1.69 [v] ------ (eq. 6. 2 ) table 13 . v ref voltage at ta = 25 c ref temp. coefficient v ref [v] 1 -0.05% / c 2.0 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 19 . internal voltage regulator circuit
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 24 in case of using internal resistors, ra and rb (intrs = "h ? ) when intrs pin is ? h ? , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2.6 3.4 4.2 5.0 5.8 6.6 7.4 8.3 table 14 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) figure 20 shows v0 voltage measured by adjusting internal regulator register ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 (1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) electr on ic volume register (0 to 63) v0 voltage [v] 63 figure 20 . v0 v oltage by 1 + (rb / ra) and electronic volume level s
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 25 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is ? l ? , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1 , 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 u a from eq. 6.1 10 = { 1 + ( rb / ra) } x v ev [v] ------ (eq. 6.3) from eq. 6. 2 v ev = { 1 - (63 - 32) / 200 } x 2.0 = 1.69 [v] ------ (eq. 6.4) from requirement 3 10 / ( ra + rb ) = 1 [ua] ------ (eq. 6.5) from equations eq. 6.3, 6.4 and 6.5 ra = 1.69 [m w ] rb = 8.31 [m w ] table 15 shows the range of v0 depending on the above requirements. table 15 . the range of v0 electronic volume level 0 ....... 32 ....... 63 v0 8.10 ....... 10.00 ....... 11.83 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and th e se output impedance are converted by the voltage follower for increasing drive capability. table 16 shows the relationship between v1 to v4 level and each duty ratio. table 16 . v1 to v4 l evel lcd bias v1 v2 v3 v4 remarks 1/n (n-1)/n x v0 (n-1)/n x v0 2/n x v0 1/n x v0 n = 4 to 11
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 26 reference circuit examples [c1 = 1.0 to 4.7 [ m f], c2 = 0.1 to 0.47 [ m f]] when using internal regulator resistors when not using internal regulator resistors v ss c1 c1 c1 c1 c1 c1 + + + + + v dd ms intrs vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c1 c1 c1 c1 c1 c1 + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss rb ra c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 ms intrs figure 21 . when using a ll lcd power circuits (6-time v/c: o n , v/r: o n , v/f: on ) when using internal regulator resistors when not using internal regulator resistors v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 ms intrs ms intrs external power supply external power supply rb ra figure 22 . when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: o n )
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 27 v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ ms intrs external power supply figure 23 . when using o nly voltage follower circuit (v/c: o ff , v/r: o ff , v/f: o n ) v ss v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ ms intrs external power supply figure 24 . when not using a ll lcd power circuits (v/c: o ff , v/r: o ff , v/f: o ff )
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 28 reset circuit setting resetb to ? l ? or reset instruction can initialize internal function. when resetb becomes ? l ? , following procedure is occurred. page address: 0 column address: 0 modify-read: off display on / off: off initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/105 reverse display on / off: o ff (normal) n-line inversion register: 0 (disable) entire display on / off: o ff (normal) power control register (vc, vr, vf) = (0, 0, 0) dc-dc step up: 3 times converter circuit = (0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register: (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) lcd bias ratio: 1/11 shl select: o ff (normal) adc select: o ff (normal) static indicator mode: o ff static indicator register: (s1, s0) = (0, 0) oscillator status: o ff power save mode: release when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 modify-read: off initial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) static indicator mode: o ff static indicator register: (s1, s0) = (0, 0) while resetb is ? l ? or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes ? l ? , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 29 instruction description table 17 . instruction table : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on res 0 0 0 0 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y7 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display on / off 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on 0 0 0 1 0 0 0 0 set initial display line register 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set initial com0 register 0 0 c6 c5 c4 c3 c2 c1 c0 2-byte in struction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set partial display duty ratio 0 0 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio 0 0 0 1 0 0 1 1 set n-line inversion 0 0 n4 n3 n2 n1 n0 2-byte i nstruction to set n-line inversion register release n-line inversion 0 0 1 1 1 0 0 1 0 0 release n-line inversion mode reverse display on / off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 30 table 17. instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc step-up 0 0 0 1 1 0 0 1 dc1 dc0 select the step-up of the internal voltage converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 ev5 ev4 ev3 ev2 ev1 ev0 2-byte i nstruction to specify the electronic volume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl select 0 0 1 1 0 0 shl com bi-directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc = 0: normal direction adc = 1: reverse direction set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator register 0 0 s1 s0 2-byte i nstruction to specify the static indicator mode oscillator on start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set power save mode 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 31 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incremented by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data d ata w rite s et c olumn a ddress s et p age a ddress o ptional s tatus c olumn = c olumn +1 n o y es d ata w rite c ontinue ? d ummy d ata r ead s et c olumn a ddress s et p age a ddress op tional s tatus c olumn = c olumn +1 n o y es d ata r ead c ontinue ? d ata r ead c olumn = c olumn +1 figure 25 . sequence for writing display data figure 26 . sequence for reading display data
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 32 read status indicates the internal status of the S6B0719 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on res 0 0 0 0 flag description busy the device is busy when internal operation or reset any instruction is rejected until busy goes low. 0: c hip is active, 1: c hip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg 15 9 ? seg0), 1: normal direction (seg0 ? seg 15 9) on indicates display on / off status 0: display on, 1: display off res indicates the initialization is in progress by resetb signal 0: c hip is active, 1: c hip is being reset. set page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age a ddress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 selected page description 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 1 0 0 1 10 1 0 1 0 1 1 1 0 1 1 1 2 accessible pages for displaying dot-matrix display data 1 1 0 0 1 3 accessible page for displaying icons 1 1 0 1 1 4 1 1 1 0 1 5 not accessible page. do not use these pages.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 33 set column address sets the c olumn a ddress of display ram from the microprocessor into the c olumn a ddress register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, c olumn a ddresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y7 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 0 0 1 1 1 0 1 15 7 1 0 0 1 1 1 1 0 15 8 1 0 0 1 1 1 1 1 15 9 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 not accessible column
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 34 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify-read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no y es change c omplete ? set column address (n) dummy read data r ead data w rite return c olumn a ddress (n) figure 27 . sequence for cursor display
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 35 display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 1 1 0 1 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i nitial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 28 . the sequence for setting the initial display line
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 36 set initial com0 register sets the initial row (com) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 : : : : : : : : 1 1 0 0 1 0 1 com101 1 1 0 0 1 1 0 com102 1 1 0 0 1 1 1 com 103 1 1 0 1 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd end 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 29 . sequence for setting the initial com0
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 37 set partial display duty ratio sets the duty ratio within range of 9 , 17 and 32 to 105 to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 1 0 0 1 1/9 0 0 1 0 0 0 1 1/1 7 0 1 0 0 0 0 0 1/ 32 0 1 0 0 0 0 1 1/ 33 : : : : : : : : 1 0 1 0 1 0 0 1/ 10 4 1 0 1 0 1 0 1 1/105 other combinations no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd end 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 30 . sequence for setting partial display
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 38 set n-line inversion register sets the inverted line number within range of 2 to 3 2 to improve the display quality by controlling the phase of the internal lcd ac signal (m) by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 2 -line inversion 0 0 0 1 0 3 -line inversion 0 0 0 1 1 4 -line inversion : : : : : : 1 1 1 0 1 3 0 -line inversion 1 1 1 1 0 3 1 -line inversion 1 1 1 1 1 3 2 -line inversion 2 nd i nstruction ( n - l ine i nversion s etting) setting n - l ine i nversion e nd 1 st i nstruction ( m ode s etting) setting n - l ine i nversion s tart figure 31 . sequence for setting partial display release n-line inversion returns to the frame inversion condition from the n-line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 39 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse d isplay on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (entire) lcd pixel is illuminated lcd pixel is illuminated power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 40 select dc/dc step-up selects one of 4 dc/dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc-dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times boosting circuit regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb / ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 41 set electronic volume register consists of 2-byte instruction. the 1 st instruction sets electronic volume mode, the 2 nd one updates the contents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 ev3 ev2 ev1 ev0 ev5 ev4 ev3 ev2 ev1 ev0 reference voltage ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd i nstruction for r egister s etting setting e lectronic v olume e nd 1 st i nstruction for m ode s etting setting e lectronic v olume s tart figure 32 . sequence for setting the electronic volume
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 42 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/10 1 1 1 1/11 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com 103 ) shl = 1: reverse direction (com 10 3 ? com0) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg 159 ) adc = 1: reverse direction (seg 15 9 ? seg0)
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 43 set static indicator state consists of two bytes instruction. the first byte instruction (set static indicator mode) enables the second byte instruction (set static indicator register) to be valid. the first byte sets the static indicator on / off. when it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1: static indicator on the 2 nd instruction: set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 0.5 second blinking) 1 0 on (about 1 second blinking ) 1 1 on (always on) oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply that is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 44 power save the S6B0719 enters the p ower s ave status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 release standby mode release sleep mode standby mode oscillator circuits : on static d river: enable lcd power supply c ircuits: off all com / seg output l evel: vss consumption current < 10 m a sleep mode oscillator c ircuits: off static driver: disable lcd power supply circuits: off all com / seg output level: vss consumption current < 2 m a set power save mode release power save mode figure 33 . power save routine
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 45 nop no n- operation rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 46 referential instruction setup flow: initializing with the built-in power supply circuits user s ystem s etup by e xternal p ins start of i nitialization power o n (vdd-vss) k eeping the resetb p in = "l" waiting for s tabilizing the p ower resetb pin = "h" user a pplication s etup by i nternal i nstructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power s etup by i nternal i nstructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for s tabilizing the lcd power levels end of i nitialization figure 34 . initializing w ith t he built- i n power supply circuits
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 47 referential instruction setup flow: initializing without the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save figure 35 . initializing without the built-in power supply circuits
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 48 referential instruction setup flow: data displaying end of i nitialization write display data by i nstruction [display data write] turn display on/off i nstruction [display on/off] end of d ata d isplay display data ram addressing by i nstruction [initial display line] [set page address] [set column address] figure 36 . data displaying r eferential instruction setup flow: power off optional status power off (vdd-vss) end of p ower o ff set power save by i nstruction figure 37 . power off
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 49 referential instruction setup flow: partial duty changing start of partial changing set display off by internal instruction [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set standby mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels figure 38 . partial duty changing
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 50 specifications absolute maximum ratings table 18 . absolute maximum ratings (vss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v0, vout + 0.3 ~ + 17 .0 v supply voltage range v1, v2, v3, v4 + 0.3 ~ v0 v external reference voltage vext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes: 1. vdd, v0, vout, v1 to v4, vext and vci are based on vss = 0v. 2. voltage vout 3 v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 51 dc characteristics table 19 . dc characteristics (v ss = 0v, v dd = 2.4 to 3.6 v, ta = -40~85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v v dd *1 operating voltage (2) v0 4.0 - 1 5 .0 v v0, *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = -0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a *3 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a *5 lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn *6 frame frequency f fr ta = 25 c 70 85 100 hz *7 fr table 20 . dc characteristi cs item symbol condition min. typ. max. unit pin used voltage converter circuit output voltage vout 3 / 4 / 5 / 6 voltage conversion (no-load ) 95 99 - % vout voltage regulator circuit operating voltage vout 6.0 - 1 7 .0 v vout voltage follower circuit operating voltage v0 4.0 - 1 5 .0 v v0 *8 reference voltage v ref ta = 25 c 1.94 2.00 2.06 v *9
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 52 dynamic current consumption (1) when an external power supply is used. table 21 . display off (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 7.0v, duty = 1/33 tbd v0 - vss = 1 0 .0v, duty = 1/65 tbd dynamic current consumption (1) i dd1 v0 - vss = 1 3 .0v, duty = 1/105 tbd m a *10 table 22 . checker pattern (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 7.0v, duty = 1/33 tbd v0 - vss = 1 0 .0v, duty = 1/65 tbd dynamic current consumption (1) i dd1 v0 - vss = 1 3 .0v, duty = 1/105 tbd m a *10 dynamic current consumption (2) when the internal power supply is on table 23 . display off (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 7.0v, x3 boosting, duty = 1/33, normal mode - - tbd v0 - vss = 7.0v, x3 boosting, duty = 1/33, high power mode - - tbd m a *10 v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/65, normal mode - - tbd v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/65, high power mode - - tbd m a *10 v0 - vss = 1 3 .0v, x 5 boosting, duty = 1/105, normal mode - - tbd dynamic current consumption (2) idd2 v0 - vss = 13 .0v, x 5 boosting, duty = 1/105, high power mode - - tbd m a *10
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 53 table 24 . check pattern (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 7.0v, x3 boosting, duty = 1/33, normal mode - - tbd v0 - vss = 7.0v, x3 boosting, duty = 1/33, high power mode - - tbd m a *10 v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/65, normal mode - - tbd v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/65, high power mode - - tbd m a *10 v0 - vss = 1 3 .0v, x 5 boosting, duty = 1/105, normal mode - - tbd dynamic current consumption (2) idd2 v0 - vss = 1 3 .0v, x 5 boosting, duty = 1/105, high power mode - - tbd m a *10 dynamic current consumption during power save mode table 25 . power save mode (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current idds1 during sleep - - 2 m a standby mode current idds2 during standby - - 10 m a
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 54 table 26 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x 4 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 9 to 105) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, ms, c68, ps, intrs, hpmb, ref, cl, m and sync. *4 . db0 to db7, fr, frs, sync, m and cl. *5 . applies when the db0 to db7, sync, m, and cl pins are in high impedance. *6 . resistance value when -0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when -0.1[ma] is applied in the on status.) *7 . see table 26 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors (rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 55 ac characteristics read / write characteristics (8080-series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwlw , t pwlr t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr cs1b rs t pwhw , t pwhr figure 39 . parallel interface (8080-series mpu) timing diagram table 27 . ac characteristics (8080-series p arallel m ode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time t cy80 300 - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw 60 60 - - ns pulse width low for read pulse width high for read e_rd (/rd) t pwlr t pwhr 120 60 - - ns data setup time data hold time t ds80 t dh80 40 15 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf - 10 140 100 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy80 - tpwlw - tpwhw ) for write, (tr + tf) < (tcy80 - tpwlr - tpwhr ) for read
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 56 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewhw , t ewhr t cy68 t ah68 t as68 db0 to db7 ( write ) db0 to db7 ( read ) e cs1b rs, r/w t ewlw , t ewlr figure 40 . parallel interface (6800-series mpu) timing diagram table 28 . ac characteristics (6800-series p arallel m ode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time t cy68 300 - ns enable width high for write enable width low for write e_rd (e) t ewhw t ewlw 60 60 - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr 120 60 - - ns data setup time data hold time t ds68 t dh68 40 15 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - 10 140 100 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy68 - tewhw - tewlw ) for write, (tr + tf) < (tcy68 - tewhr - tewlr ) for read
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 57 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = 1 ) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 41 . serial interface timing diagram table 29 . ac characteristics (serial mode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw 250 100 100 - - - ns address setup time address hold time rs t ass t ahs 150 150 - - ns data setup time data hold time db7 (sid) t dss t dhs 100 100 - - ns cs1b setup time cs1b hold time cs1b t css t chs 150 150 - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 58 reset input timing resetb internal status t rw t r reset complete during reset figure 42 . reset input timing diagram table 30 . ac characteristics (reset mode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1000 - ns reset time - t r - 1000 ns
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 59 reference applications microprocessor interface db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 071 9 figure 43 . in case of interfacing with 6800-series (ps = ? h ? , c68 = ? h ? ) db0 to db7 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 071 9 figure 44 . in case of interfacing with 8080-series (ps = ? h ? , c68 = ? l ? ) open resetb vss vdd or vss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s6b 071 9 figure 45 . in case of serial interface (ps = ? l ? , c68 = ? h/l ? )
1 60 seg / 105 com driver & controller for stn lcd preliminary spec. ver. 0. 4 S6B0719 60 connections between S6B0719 and lcd panel single chip configuration (1/105 duty configurations) com51 - com0 coms coms com 10 3 - com 5 2 seg 15 9 seg 15 8 ? seg1 seg0 s6b 071 9 (bottom view) com 5 1 - com0 coms coms com 10 3 - com 5 2 seg0 seg1 ? seg 15 8 seg 15 9 s6b 071 9 (top view) ? a x a ? a x a 10 4 1 6 0 pixels ? a x a ? a x a 10 4 1 6 0 pixels figure 46 . shl = 0, adc = 0 figure 47 . shl = 0, adc = 1 com52 com103 coms coms com0 com 5 1 seg 15 9 seg 15 8 ? seg1 seg0 s6b 071 9 (top view) coms com0 com 5 1 com 5 2 com 10 3 coms seg0 seg1 ? seg 15 8 seg 15 9 s6b 071 9 (bottom view) ? a x a ? a x a 10 4 1 6 0 pixels ? a x a ? a x a 10 4 1 6 0 pixels figure 48 . shl = 1, adc = 0 figure 49 . shl = 1, adc = 1
S6B0719 preliminary spec. ver. 0 . 4 160 seg / 105 com driver & controller for stn lcd 61 multiple c hip configuration com51 - com0 coms coms com 10 3 - com 5 2 seg 15 9 seg 15 8 ? seg1 seg0 s6b 071 9 (bottom view) (master) com 5 1 - com0 coms coms com 10 3 - com52 seg 15 9 seg 15 8 ? seg1 seg0 s6b0 71 9 (bottom view) (slave) ? a x a ? a x a 10 4 32 0 pixels figure 50 . shl = 0, adc = 1 connect the following pins of two chips each other: - display clock pins: cl, m, sync - lcd power pins: v0, v1, v2, v3, v4 ? a x a ? a x a 10 4 32 0 pixels com 5 2 com 10 3 coms coms com0 com 5 1 seg0 seg1 ? seg158 seg15 9 s6b 071 9 (bottom view) (master) com 5 2 com 10 3 coms coms com0 com51 seg0 seg1 ? seg 15 8 seg 15 9 s6b 071 9 (bottom view) (slave) figure 51 . shl = 1, adc = 0 connect the following pins of two chips each other: - display clock pins: cl, m, sync - lcd power pins: v0, v1, v2, v3, v4

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